An efficient 2D router architecture for extending the performance of inhomogeneous 3D NoC-based multi-core architectures

To meet the performance and scalability demands of the fast-paced technological growth towards exascale and Big-Data processing with the performance bottleneck of conventional metal based interconnects, alternative interconnect fabrics such as inhomogeneous three dimensional integrated Network-on-Chip (3D NoC) has emanated as a cost-effective solution for emerging multi-core design. However, these interconnects trade-off optimized performance for cost by restricting the number of area and power hungry 3D routers. Consequently, in this paper, we propose a low-latency adaptive router with a low-complexity single-cycle bypassing mechanism to alleviate the performance degradation due to the slow 2D routers in inhomogeneous 3D NoCs. By combining the low-complexity bypassing technique with adaptive routing, the proposed router is able to balance the traffic in the network to reduce the average packet latency under various traffic loads. Simulation shows that, the proposed router can reduce the average packet delay by an average of 45% in 3D NoCs

A survey of emerging architectural techniques for improving cache energy consumption

The search goes on for another ground breaking phenomenon to reduce the ever-increasing disparity between the CPU performance and storage. There are encouraging breakthroughs in enhancing CPU performance through fabrication technologies and changes in chip designs but not as much luck has been struck with regards to the computer storage resulting in material negative system performance. A lot of research effort has been put on finding techniques that can improve the energy efficiency of cache architectures. This work is a survey of energy saving techniques which are grouped on whether they save the dynamic energy, leakage energy or both. Needless to mention, the aim of this work is to compile a quick reference guide of energy saving techniques from 2013 to 2016 for engineers, researchers and students

A study of recent contributions on performance and simulation techniques for accelerator devices

High performance computing platform is moving from homogeneous individual unites to heterogeneous systems where each unit is a combination of homogeneous cores and accelerator devices. Accelerators such as GPUs, FPGAs, DSPs, are usually designed for specific and intensive type of computing tasks. The presence of these devises have created fresh and attractive development platforms for developers and designers as well as novel performance analysis frameworks and optimization tools. This is the cutting edge in performance of some accelerator devices like: GPUs and Intel’s Xeon Phi. We outline some of the existing heterogeneous systems and their development frameworks. The core of this study is a review of performance modeling of these devices

A study of FPGA-based System-on-Chip designs for real-time industrial application

This paper shows the benefits of the Field Programming Gate Array (FPGAs) in industrial control applications. The author starts by addressing the benefits of FPGA and where it is useful. As well as, the author has done some FPGA’s evaluation researches on the FPGA performing explaining the performance of the FPGA and the design tools. To show the benefits of the FPGA, an industrial application example has been used. The application is a real-time face detection and tracking using FPGA. Face tracking will depend on calculating the centroid of each detected region. A DE2-SoC Altera board has been used to implement this application. The application based on few algorithms that filter the captured images to detect them. These algorithms have been translated to a Verilog code to run it on the DE2-SoC boar

Exploring the Relationship Between Language Barrier and the Poor Performance of BAME/International Students in the United Kingdom Universities

In recent years, the number of BAME/International students has been on a steady increase as many migrate from their home countries into the United Kingdom to advance their graduate studies in British universities. In spite that most BAME students migrate to the United Kingdom for the purpose of education, their poor academic performance has however been an observable trend. While many works of literature have sought to investigate the reasons behind this unpleasant trend, some have offered a very interesting perspective to the discourse as to the fact that BAME students experience some obstacles which partially affect them in adjusting to the environmental, educational, and cultural lifestyle. Notably, the obstacles affect the BAME students’ chances of graduating with good grades than their British colleagues in UK universities. While this is believed mostly amongst BAME students, it remains, at best, a conjecture. Thus, this study shall examine how BAME students from Asian and African nations change when they enrol in a campus-based university in the UK to pursue their diverse academic goals. To achieve this, quantitative and qualitative research methods will be adopted to empirically explore the language barrier, cultural differences, and issues encountered by the BAME students at postgraduate level in the UK universities. Furthermore, a face-to-face interview and questionnaires will be adopted to gather data from students in the College. Survey and interview questions will be shared amongst students to ascertain their perception of schooling, grade performance in respect to the challenge

Thematic analysis of female software developers’ workplace experience in Nigerian companies

The low representation of women working as software developers around the globe has been a significant issue over the years especially in a developing country like Nigeria. This inadequate representation leads to software applications and programs being partial to end-users along with preventing women from benefiting from one of the current most lucrative career opportunity. Some Software development start-ups in Nigeria have received about $1.8 billion in funding in the year 2021 and just 27% of the start-ups that received the money have at least one woman as a founding member. Different barriers have been in existence to discourage women from pursuing a career in the field worldwide like a glass ceiling, and significant pay gap against the male counterparts. These barriers are now being lifted at a slow rate with the help of different Non-Governmental Organisations (NGOs). The aim of this study was to interpret and understand the different experiences some of the few female programmers have had around the workplace while working for Nigerian companies. A pilot study was conducted among 6 female programmers in order to improve the questionnaire. The final questionnaire was sent out via LinkedIn, WhatsApp and Twitter to some female programmers but only 6 responded. A thematic analysis was conducted from the information the various participants submitted to locate and understand the recurring themes amongst their experiences. The thematic analysis revealed 4 key themes which includes: Career transition; Financial stability; fulfilment; work life balance; Professional Culture & Gender stereotype and Fulfilment. Most women stated they transitioned into the programming space after coming across the information from friends and family. The major influence was the financial stability and the fulfilment of solving problems the field provide. Their experience has been negatively influenced by the poor work life the field provided. Gender stereotype was also highlighted as a core reason as why other women do not venture into the space

A study of recent contributions on simulation tools for Network-on-Chip (NoC)

The growth in the number of Intellectual Properties (IPs) or the number of cores on the same chip becomes a critical issue in System-on-Chip (SoC) due to the intra-communication problem between the chip elements. As a result, Network-on-Chip (NoC) has emerged as a new system architecture to overcome intra-communication issues. New approaches and methodologies have been developed by many researchers to improve NoC. Also, many NoC simulation tools have been proposed and adopted by both academia and industry. This paper presents a study of recent contributions on simulation tools for NoC. Furthermore, an overview of NoC is covered as well as a comparison between some NoC simulators to help facilitate research in on-chip communication

A survey of recent contributions of high performance NoC architectures

The Network-on-Chip (NoC) paradigm has been herald as the solution to the communication limitation that System-On-Chip (SoC) poses. However, power consumption is one of its major defects. To ensure that a high performance architecture is constructed, analyzing how power can be reduced in each area of the network is essential. Power dissipation can be reduced by adjustments to the routers, the architecture itself and the communication links. In this paper, a survey is conducted on recent contributions and techniques employed by researchers towards the reduction of power in the router architecture, network architecture and communication links

Energy and performance-aware application mapping for inhomogeneous 3D networks-on-chip

Three dimensional Networks-on-Chip (3D NoCs) have evolved as an ideal solution to the communication demands and complexity of future high density many core architectures. However, the design practicality of 3D NoCs faces several challenges such as thermal issues, high power consumption and area overhead of 3D routers as well as high complexity and cost of vertical link implementation. To mitigate the performance and manufacturing cost of 3D NoCs, inhomogeneous architectures have emerged to combine 2D and 3D routers in 3D NoCs producing lower area and energy consumption while maintaining the performance of homogeneous 3D NoCs. Due to the limited number of vertical links, application mapping on inhomogeneous 3D NoCs can be complex. However, application mapping has a great impact on the performance and energy consumption of NoCs. This paper presents an energy and performance aware application mapping algorithm for inhomogeneous 3D NoCs. The algorithm has been evaluated with various realistic traffic patterns and compared with existing mapping algorithms. Experimental results show NoCs mapped with the proposed algorithm have lower energy consumption and significant reduction in packet delays compared to the existing algorithms and comparable average packet latency with Branch-and-Bound